Pretty cool stuff coming in the next version of the Intel instruction set.
One cool feature is the ability to take coarse locks (think locking an entire Abstract Data Structure) and having the hardware give performance similar to fine grain locks by allowing multiple threads to enter the mutex but guaranteeing they will abort (and presumably retry with the lock enforced) if they cause side-effects to one another.
One cool feature is the ability to take coarse locks (think locking an entire Abstract Data Structure) and having the hardware give performance similar to fine grain locks by allowing multiple threads to enter the mutex but guaranteeing they will abort (and presumably retry with the lock enforced) if they cause side-effects to one another.
Transactional memory going mainstream with Intel Haswell
